xilinx.com project coregen 1.0 adc_serdes NONE RETIMED NONE C0 NONE 8 DIFF NONE 0 0 SINGLE false DIFF 0 None SAME_EDGE_PIPELINED NONE 0 SAME_EDGE LVCMOS25 INPUTS NOT_APP false true 9 NETWORKING true NOT_APP LVDS_25 0 RISING LVCMOS18 BUFIO BUFPLL 0 SDR coregen ./ ./tmp/ ./tmp/_cg xc6slx45t spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL false adc_sync_fifo false false 12 3 65 16 true No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false false 1 Active_High 4 false 4 16 0 true true Active_High Active_High false false false No_Programmable_Full_Threshold false 4 Asynchronous_Reset Standard_FIFO 13 true false false 1 Active_High false 2 65 1 false coregen ./ ./tmp/ ./tmp/_cg xc6slx45t spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL false test_dpram 0 false 1024 false WRITE_FIRST WRITE_FIRST false false 32 32 false false 8kx2 Simple_Dual_Port_RAM false 9 false 0 false 0 false false false Always_Enabled Always_Enabled 100 false false false false 50 Minimum_Area false No_ECC 100 false 100 32 32 SYNC false false 100 0 0 false false no_coe_file_loaded Single_Bit_Error_Injection ALL CE CE coregen ./ ./tmp/ ./tmp/_cg xc6slx45t spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL false wb_ddr_fifo false false 1021 3 64 1024 true No_Programmable_Empty_Threshold false false Common_Clock_Block_RAM false false 0 Active_High 10 false 10 1024 0 true true Active_High Active_High false false false No_Programmable_Full_Threshold false 10 Asynchronous_Reset Standard_FIFO 1022 true false false 1 Active_High false 2 64 1 false coregen ./ ./tmp/ ./tmp/_cg xc6slx45t spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL false wb_sync_fifo false false 1020 3 32 1024 true No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false false 1 Active_High 10 false 10 2048 0 true true Active_High Active_High false false false No_Programmable_Full_Threshold false 11 Asynchronous_Reset Standard_FIFO 1021 true false false 1 Active_High false 2 64 1 false coregen ./ ./tmp/ ./tmp/_cg xc6slx45t spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL false multishot_dpram 0 false 8192 READ_FIRST false READ_FIRST false false 64 64 false false 8kx2 Simple_Dual_Port_RAM false 9 false 0 false 0 false false false Always_Enabled Always_Enabled 100 false false true false 50 Minimum_Area false No_ECC 100 false 100 64 64 SYNC false false 100 0 0 false false no_coe_file_loaded Single_Bit_Error_Injection ALL CE CE coregen ./ ./tmp/ ./tmp/_cg xc6slx45t spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL false customization_generator ip_xco_generator ./multishot_dpram.xco xco Fri Apr 01 12:12:43 GMT 2011 0x720C9A71 implementation_netlist_generator ./blk_mem_gen_ds512.pdf pdf Fri Apr 01 12:14:22 GMT 2011 0xB7558D4E ./blk_mem_gen_readme.txt txt Fri Apr 01 12:14:22 GMT 2011 0x4F6653C3 ./multishot_dpram.asy asy Fri Apr 01 12:12:48 GMT 2011 0x2537E763 ./multishot_dpram.ngc ngc Fri Apr 01 12:14:38 GMT 2011 0x5FEFC1FA ./multishot_dpram.sym asy unknown Fri Apr 01 12:14:23 GMT 2011 0x20CC10EA ./multishot_dpram.vhd vhdl Fri Apr 01 12:14:23 GMT 2011 0x2AAD994E ./multishot_dpram.vho vho Fri Apr 01 12:14:23 GMT 2011 0x04A5E303 instantiation_template_generator ./multishot_dpram.vho vho Fri Apr 01 12:14:39 GMT 2011 0x04A5E303 xco_generator ./multishot_dpram.xco xco Fri Apr 01 12:14:44 GMT 2011 0xCF69D4C5 xmdf_generator ./multishot_dpram_xmdf.tcl tclXmdf tcl Fri Apr 01 12:14:44 GMT 2011 0x8AC6FD5A ise_generator ./_xmsgs/pn_parser.xmsgs ignore unknown Fri Apr 01 12:14:57 GMT 2011 0xB31BC6A0 ./multishot_dpram.gise ignore gise Fri Apr 01 12:14:57 GMT 2011 0xDE324B66 ./multishot_dpram.xise ignore xise Fri Apr 01 12:14:57 GMT 2011 0x9F89D5BA deliver_readme_generator flist_generator ./multishot_dpram_flist.txt ignore txtFlist txt Fri Apr 01 12:14:58 GMT 2011 0xC11F7F2D view_readme_generator coregen ./ ./tmp/ ./tmp/_cg xc6slx45t spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL false