-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- The following code must appear in the VHDL architecture header: ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG component adc_serdes generic (-- width of the data for the system sys_w : integer := 9; -- width of the data for the device dev_w : integer := 72); port ( -- From the system into the device DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0); DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0); DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0); BITSLIP : in std_logic; -- Clock and reset signals CLK_IN : in std_logic; -- Fast clock from PLL/MMCM CLK_DIV_IN : in std_logic; -- Slow clock from PLL/MMCM LOCKED_IN : in std_logic; LOCKED_OUT : out std_logic; CLK_RESET : in std_logic; -- Reset signal for Clock circuit IO_RESET : in std_logic); -- Reset signal for IO circuit end component; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ -- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG None your_instance_name : adc_serdes port map ( -- From the system into the device DATA_IN_FROM_PINS_P => DATA_IN_FROM_PINS_P, DATA_IN_FROM_PINS_N => DATA_IN_FROM_PINS_N, DATA_IN_TO_DEVICE => DATA_IN_TO_DEVICE, BITSLIP => BITSLIP, -- Clock and reset signals CLK_IN => CLK_IN, CLK_DIV_IN => CLK_DIV_IN, LOCKED_IN => LOCKED_IN, LOCKED_OUT => LOCKED_OUT, CLK_RESET => CLK_RESET, IO_RESET => IO_RESET); -- INST_TAG_END ------ End INSTANTIATION Template ------------