fmc_adc_100Ms_csr

FMC ADC 100MS/s core registers

Wishbone slave for FMC ADC 100MS/s core

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control register
3.2. Status register
3.3. Trigger configuration
3.4. Trigger delay
3.5. Software trigger
3.6. Number of shots
3.7. Trigger UTC tag (LSBs)
3.8. Trigger UTC tag (MSBs)
3.9. Start UTC tag (LSBs)
3.10. Start UTC tag (MSBs)
3.11. Stop UTC tag (LSBs)
3.12. Stop UTC tag (MSBs)
3.13. Sample rate
3.14. Pre-trigger samples
3.15. Post-trigger samples
3.16. Sample counter
3.17. Solid state relays control for channel 1
3.18. Channel 1 current value
3.19. Solid state relays control for channel 2
3.20. Channel 2 current value
3.21. Solid state relays control for channel 3
3.22. Channel 3 current value
3.23. Solid state relays control for channel 4
3.24. Channel 4 current value

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	Control register	fmc_adc_core_ctl	CTL
0x1	REG	Status register	fmc_adc_core_sta	STA
0x2	REG	Trigger configuration	fmc_adc_core_trig_cfg	TRIG_CFG
0x3	REG	Trigger delay	fmc_adc_core_trig_dly	TRIG_DLY
0x4	REG	Software trigger	fmc_adc_core_sw_trig	SW_TRIG
0x5	REG	Number of shots	fmc_adc_core_shots	SHOTS
0x6	REG	Trigger UTC tag (LSBs)	fmc_adc_core_trig_utc_l	TRIG_UTC_L
0x7	REG	Trigger UTC tag (MSBs)	fmc_adc_core_trig_utc_h	TRIG_UTC_H
0x8	REG	Start UTC tag (LSBs)	fmc_adc_core_start_utc_l	START_UTC_L
0x9	REG	Start UTC tag (MSBs)	fmc_adc_core_start_utc_h	START_UTC_H
0xa	REG	Stop UTC tag (LSBs)	fmc_adc_core_stop_utc_l	STOP_UTC_L
0xb	REG	Stop UTC tag (MSBs)	fmc_adc_core_stop_utc_h	STOP_UTC_H
0xc	REG	Sample rate	fmc_adc_core_sr	SR
0xd	REG	Pre-trigger samples	fmc_adc_core_pre_samples	PRE_SAMPLES
0xe	REG	Post-trigger samples	fmc_adc_core_post_samples	POST_SAMPLES
0xf	REG	Sample counter	fmc_adc_core_samp_cnt	SAMP_CNT
0x10	REG	Solid state relays control for channel 1	fmc_adc_core_ch1_ssr	CH1_SSR
0x11	REG	Channel 1 current value	fmc_adc_core_ch1_val	CH1_VAL
0x12	REG	Solid state relays control for channel 2	fmc_adc_core_ch2_ssr	CH2_SSR
0x13	REG	Channel 2 current value	fmc_adc_core_ch2_val	CH2_VAL
0x14	REG	Solid state relays control for channel 3	fmc_adc_core_ch3_ssr	CH3_SSR
0x15	REG	Channel 3 current value	fmc_adc_core_ch3_val	CH3_VAL
0x16	REG	Solid state relays control for channel 4	fmc_adc_core_ch4_ssr	CH4_SSR
0x17	REG	Channel 4 current value	fmc_adc_core_ch4_val	CH4_VAL

2. HDL symbol

→	rst_n_i	Control register:
→	wb_clk_i	fmc_adc_core_ctl_fsm_cmd_o[1:0]	⇒
⇒	wb_addr_i[4:0]	fmc_adc_core_ctl_fsm_cmd_wr_o	→
⇒	wb_data_i[31:0]	fmc_adc_core_ctl_fmc_clk_oe_o	→
⇐	wb_data_o[31:0]	fmc_adc_core_ctl_offset_dac_clr_n_o	→
→	wb_cyc_i	fmc_adc_core_ctl_man_bitslip_o	→
⇒	wb_sel_i[3:0]	fmc_adc_core_ctl_test_data_en_o	→
→	wb_stb_i	fmc_adc_core_ctl_trig_led_o	→
→	wb_we_i	fmc_adc_core_ctl_acq_led_o	→
←	wb_ack_o
→	fs_clk_i	Status register:
		fmc_adc_core_sta_fsm_i[2:0]	⇐
		fmc_adc_core_sta_serdes_pll_i	←
		fmc_adc_core_sta_serdes_synced_i	←

		Trigger configuration:
		fmc_adc_core_trig_cfg_hw_trig_sel_o	→
		fmc_adc_core_trig_cfg_ext_trig_pol_o	→
		fmc_adc_core_trig_cfg_hw_trig_en_o	→
		fmc_adc_core_trig_cfg_sw_trig_en_o	→
		fmc_adc_core_trig_cfg_int_trig_sel_o[1:0]	⇒
		fmc_adc_core_trig_cfg_dummy_o[9:0]	⇒
		fmc_adc_core_trig_cfg_int_trig_thres_o[15:0]	⇒

		Trigger delay:
		fmc_adc_core_trig_dly_o[31:0]	⇒

		Software trigger:
		fmc_adc_core_sw_trig_o[31:0]	⇒
		fmc_adc_core_sw_trig_wr_o	→

		Number of shots:
		fmc_adc_core_shots_nb_o[15:0]	⇒

		Trigger UTC tag (LSBs):
		fmc_adc_core_trig_utc_l_i[31:0]	⇐

		Trigger UTC tag (MSBs):
		fmc_adc_core_trig_utc_h_i[31:0]	⇐

		Start UTC tag (LSBs):
		fmc_adc_core_start_utc_l_i[31:0]	⇐

		Start UTC tag (MSBs):
		fmc_adc_core_start_utc_h_i[31:0]	⇐

		Stop UTC tag (LSBs):
		fmc_adc_core_stop_utc_l_i[31:0]	⇐

		Stop UTC tag (MSBs):
		fmc_adc_core_stop_utc_h_i[31:0]	⇐

		Sample rate:
		fmc_adc_core_sr_deci_o[15:0]	⇒

		Pre-trigger samples:
		fmc_adc_core_pre_samples_o[31:0]	⇒

		Post-trigger samples:
		fmc_adc_core_post_samples_o[31:0]	⇒

		Sample counter:
		fmc_adc_core_samp_cnt_i[31:0]	⇐

		Solid state relays control for channel 1:
		fmc_adc_core_ch1_ssr_o[6:0]	⇒

		Channel 1 current value:
		fmc_adc_core_ch1_val_i[15:0]	⇐

		Solid state relays control for channel 2:
		fmc_adc_core_ch2_ssr_o[6:0]	⇒

		Channel 2 current value:
		fmc_adc_core_ch2_val_i[15:0]	⇐

		Solid state relays control for channel 3:
		fmc_adc_core_ch3_ssr_o[6:0]	⇒

		Channel 3 current value:
		fmc_adc_core_ch3_val_i[15:0]	⇐

		Solid state relays control for channel 4:
		fmc_adc_core_ch4_ssr_o[6:0]	⇒

		Channel 4 current value:
		fmc_adc_core_ch4_val_i[15:0]	⇐

3. Register description

3.1. Control register

HW prefix:	fmc_adc_core_ctl
HW address:	0x0
C prefix:	CTL
C offset:	0x0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
ACQ_LED	TRIG_LED	TEST_DATA_EN	MAN_BITSLIP	OFFSET_DAC_CLR_N	FMC_CLK_OE	FSM_CMD[1:0]

FSM_CMD [read/write]: State machine commands
1: start
2: stop
FMC_CLK_OE [read/write]: FMC Si750 output enable
OFFSET_DAC_CLR_N [read/write]: Offset DACs clear (active low)
MAN_BITSLIP [write-only]: Manual serdes bitslip
TEST_DATA_EN [read/write]: Enable test data
Write the address counter value instead of ADC data to DDR
TRIG_LED [read/write]: Manual TRIG LED
Manual control of the front panel TRIG LED
ACQ_LED [read/write]: Manual ACQ LED
Manual control of the front panel ACQ LED

3.2. Status register

HW prefix:	fmc_adc_core_sta
HW address:	0x1
C prefix:	STA
C offset:	0x4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	SERDES_SYNCED	SERDES_PLL	FSM[2:0]

FSM [read-only]: State machine status
SERDES_PLL [read-only]: SerDes PLL status
SERDES_SYNCED [read-only]: SerDes synchronization status
0: bitslip in progress
1: serdes synchronized

3.3. Trigger configuration

HW prefix:	fmc_adc_core_trig_cfg
HW address:	0x2
C prefix:	TRIG_CFG
C offset:	0x8

31	30	29	28	27	26	25	24
INT_TRIG_THRES[15:8]

23	22	21	20	19	18	17	16
INT_TRIG_THRES[7:0]

15	14	13	12	11	10	9	8
DUMMY[9:2]

7	6	5	4	3	2	1	0
DUMMY[1:0]		INT_TRIG_SEL[1:0]		SW_TRIG_EN	HW_TRIG_EN	EXT_TRIG_POL	HW_TRIG_SEL

HW_TRIG_SEL [read/write]: Hardware trigger selection
0: internal (data threshold)
1: external (front panel trigger input)
EXT_TRIG_POL [read/write]: External hardware trigger polarity
0: positive edge
1: negative edge
HW_TRIG_EN [read/write]: Hardware trigger enable
0: disable
1: enable
SW_TRIG_EN [read/write]: Software trigger enable
0: disable
1: enable
INT_TRIG_SEL [read/write]: Channel selection for internal trigger
00: channel 1
01: channel 2
10: channel 3
11: channel 4
DUMMY [read/write]: Dummy
Ignore on read, write with 0's
INT_TRIG_THRES [read/write]: Threshold for internal trigger
Treated as two's complement and compared to raw ADC data

3.4. Trigger delay

HW prefix:	fmc_adc_core_trig_dly
HW address:	0x3
C prefix:	TRIG_DLY
C offset:	0xc

31	30	29	28	27	26	25	24
TRIG_DLY[31:24]

23	22	21	20	19	18	17	16
TRIG_DLY[23:16]

15	14	13	12	11	10	9	8
TRIG_DLY[15:8]

7	6	5	4	3	2	1	0
TRIG_DLY[7:0]

TRIG_DLY [read/write]: Trigger delay value
Delay to apply on the trigger in sampling clock ticks

3.5. Software trigger

HW prefix:	fmc_adc_core_sw_trig
HW address:	0x4
C prefix:	SW_TRIG
C offset:	0x10

Writing (anything) to this register generates a software trigger

31	30	29	28	27	26	25	24
SW_TRIG[31:24]

23	22	21	20	19	18	17	16
SW_TRIG[23:16]

15	14	13	12	11	10	9	8
SW_TRIG[15:8]

7	6	5	4	3	2	1	0
SW_TRIG[7:0]

SW_TRIG [write-only]: Software trigger

3.6. Number of shots

HW prefix:	fmc_adc_core_shots
HW address:	0x5
C prefix:	SHOTS
C offset:	0x14

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
NB[15:8]

7	6	5	4	3	2	1	0
NB[7:0]

NB [read/write]: Number of shots
Number of shots required in multi-shot mode, set to one for single-shot mode

3.7. Trigger UTC tag (LSBs)

HW prefix:	fmc_adc_core_trig_utc_l
HW address:	0x6
C prefix:	TRIG_UTC_L
C offset:	0x18

31	30	29	28	27	26	25	24
TRIG_UTC_L[31:24]

23	22	21	20	19	18	17	16
TRIG_UTC_L[23:16]

15	14	13	12	11	10	9	8
TRIG_UTC_L[15:8]

7	6	5	4	3	2	1	0
TRIG_UTC_L[7:0]

TRIG_UTC_L [read-only]: Trigger UTC tag (LSBs)
UTC time tag (LSBs) of the last trigger, inlcuding the trigger delay

3.8. Trigger UTC tag (MSBs)

HW prefix:	fmc_adc_core_trig_utc_h
HW address:	0x7
C prefix:	TRIG_UTC_H
C offset:	0x1c

31	30	29	28	27	26	25	24
TRIG_UTC_H[31:24]

23	22	21	20	19	18	17	16
TRIG_UTC_H[23:16]

15	14	13	12	11	10	9	8
TRIG_UTC_H[15:8]

7	6	5	4	3	2	1	0
TRIG_UTC_H[7:0]

TRIG_UTC_H [read-only]: Trigger UTC tag (MSBs)
UTC time tag (MSBs) of the last trigger, inlcuding the trigger delay

3.9. Start UTC tag (LSBs)

HW prefix:	fmc_adc_core_start_utc_l
HW address:	0x8
C prefix:	START_UTC_L
C offset:	0x20

31	30	29	28	27	26	25	24
START_UTC_L[31:24]

23	22	21	20	19	18	17	16
START_UTC_L[23:16]

15	14	13	12	11	10	9	8
START_UTC_L[15:8]

7	6	5	4	3	2	1	0
START_UTC_L[7:0]

START_UTC_L [read-only]: Start UTC tag (LSBs)
UTC time tag (LSBs) of the last start

3.10. Start UTC tag (MSBs)

HW prefix:	fmc_adc_core_start_utc_h
HW address:	0x9
C prefix:	START_UTC_H
C offset:	0x24

31	30	29	28	27	26	25	24
START_UTC_H[31:24]

23	22	21	20	19	18	17	16
START_UTC_H[23:16]

15	14	13	12	11	10	9	8
START_UTC_H[15:8]

7	6	5	4	3	2	1	0
START_UTC_H[7:0]

START_UTC_H [read-only]: Start UTC tag (MSBs)
UTC time tag (MSBs) of the last start

3.11. Stop UTC tag (LSBs)

HW prefix:	fmc_adc_core_stop_utc_l
HW address:	0xa
C prefix:	STOP_UTC_L
C offset:	0x28

31	30	29	28	27	26	25	24
STOP_UTC_L[31:24]

23	22	21	20	19	18	17	16
STOP_UTC_L[23:16]

15	14	13	12	11	10	9	8
STOP_UTC_L[15:8]

7	6	5	4	3	2	1	0
STOP_UTC_L[7:0]

STOP_UTC_L [read-only]: Stop UTC tag (LSBs)
UTC time tag (LSBs) of the last stop

3.12. Stop UTC tag (MSBs)

HW prefix:	fmc_adc_core_stop_utc_h
HW address:	0xb
C prefix:	STOP_UTC_H
C offset:	0x2c

31	30	29	28	27	26	25	24
STOP_UTC_H[31:24]

23	22	21	20	19	18	17	16
STOP_UTC_H[23:16]

15	14	13	12	11	10	9	8
STOP_UTC_H[15:8]

7	6	5	4	3	2	1	0
STOP_UTC_H[7:0]

STOP_UTC_H [read-only]: Stop UTC tag (MSBs)
UTC time tag (MSBs) of the last stop

3.13. Sample rate

HW prefix:	fmc_adc_core_sr
HW address:	0xc
C prefix:	SR
C offset:	0x30

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
DECI[15:8]

7	6	5	4	3	2	1	0
DECI[7:0]

DECI [read/write]: Sample rate decimation
Decimation factor

3.14. Pre-trigger samples

HW prefix:	fmc_adc_core_pre_samples
HW address:	0xd
C prefix:	PRE_SAMPLES
C offset:	0x34

31	30	29	28	27	26	25	24
PRE_SAMPLES[31:24]

23	22	21	20	19	18	17	16
PRE_SAMPLES[23:16]

15	14	13	12	11	10	9	8
PRE_SAMPLES[15:8]

7	6	5	4	3	2	1	0
PRE_SAMPLES[7:0]

PRE_SAMPLES [read/write]: Pre-trigger samples
Number of requested pre-trigger samples

3.15. Post-trigger samples

HW prefix:	fmc_adc_core_post_samples
HW address:	0xe
C prefix:	POST_SAMPLES
C offset:	0x38

31	30	29	28	27	26	25	24
POST_SAMPLES[31:24]

23	22	21	20	19	18	17	16
POST_SAMPLES[23:16]

15	14	13	12	11	10	9	8
POST_SAMPLES[15:8]

7	6	5	4	3	2	1	0
POST_SAMPLES[7:0]

POST_SAMPLES [read/write]: Post-trigger samples
Number of requested post-trigger samples

3.16. Sample counter

HW prefix:	fmc_adc_core_samp_cnt
HW address:	0xf
C prefix:	SAMP_CNT
C offset:	0x3c

31	30	29	28	27	26	25	24
SAMP_CNT[31:24]

23	22	21	20	19	18	17	16
SAMP_CNT[23:16]

15	14	13	12	11	10	9	8
SAMP_CNT[15:8]

7	6	5	4	3	2	1	0
SAMP_CNT[7:0]

SAMP_CNT [read-only]: Sample counter
Counts the number of sample.
It is reset on START and then counts the number of pre-trigger + post-trigger samples

3.17. Solid state relays control for channel 1

HW prefix:	fmc_adc_core_ch1_ssr
HW address:	0x10
C prefix:	CH1_SSR
C offset:	0x40

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	CH1_SSR[6:0]

CH1_SSR [read/write]: Solid state relays control for channel 1
Controls input voltage range, termination and DC offset error calibration

3.18. Channel 1 current value

HW prefix:	fmc_adc_core_ch1_val
HW address:	0x11
C prefix:	CH1_VAL
C offset:	0x44

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
CH1_VAL[15:8]

7	6	5	4	3	2	1	0
CH1_VAL[7:0]

CH1_VAL [read-only]: Channel 1 current value
Current ADC raw value

3.19. Solid state relays control for channel 2

HW prefix:	fmc_adc_core_ch2_ssr
HW address:	0x12
C prefix:	CH2_SSR
C offset:	0x48

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	CH2_SSR[6:0]

CH2_SSR [read/write]: Solid state relays control for channel 2
Controls input voltage range, termination and DC offset error calibration

3.20. Channel 2 current value

HW prefix:	fmc_adc_core_ch2_val
HW address:	0x13
C prefix:	CH2_VAL
C offset:	0x4c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
CH2_VAL[15:8]

7	6	5	4	3	2	1	0
CH2_VAL[7:0]

CH2_VAL [read-only]: Channel 2 current value
Current ADC raw value

3.21. Solid state relays control for channel 3

HW prefix:	fmc_adc_core_ch3_ssr
HW address:	0x14
C prefix:	CH3_SSR
C offset:	0x50

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	CH3_SSR[6:0]

CH3_SSR [read/write]: Solid state relays control for channel 3
Controls input voltage range, termination and DC offset error calibration

3.22. Channel 3 current value

HW prefix:	fmc_adc_core_ch3_val
HW address:	0x15
C prefix:	CH3_VAL
C offset:	0x54

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
CH3_VAL[15:8]

7	6	5	4	3	2	1	0
CH3_VAL[7:0]

CH3_VAL [read-only]: Channel 3 current value
Current ADC raw value

3.23. Solid state relays control for channel 4

HW prefix:	fmc_adc_core_ch4_ssr
HW address:	0x16
C prefix:	CH4_SSR
C offset:	0x58

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	CH4_SSR[6:0]

CH4_SSR [read/write]: Solid state relays control for channel 4
Controls input voltage range, termination and DC offset error calibration

3.24. Channel 4 current value

HW prefix:	fmc_adc_core_ch4_val
HW address:	0x17
C prefix:	CH4_VAL
C offset:	0x5c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
CH4_VAL[15:8]

7	6	5	4	3	2	1	0
CH4_VAL[7:0]

CH4_VAL [read-only]: Channel 4 current value
Current ADC raw value

fmc_adc_100Ms_csr

FMC ADC 100MS/s core registers

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