CERN FMC ADC 100M 14b 4cha solderpad
cern-fmc-adc-100m-14b-4cha / hdl / spec / ip_cores / multishot_dpram.vho
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation, implementation and creation of -- -- design files limited to Xilinx devices or technologies. Use -- -- with non-Xilinx devices or technologies is expressly prohibited -- -- and immediately terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- -- FOR A PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support -- -- appliances, devices, or systems. Use in such applications are -- -- expressly prohibited. -- -- -- -- (c) Copyright 1995-2009 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -- The following code must appear in the VHDL architecture header: ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG component multishot_dpram port ( clka: IN std_logic; wea: IN std_logic_VECTOR(0 downto 0); addra: IN std_logic_VECTOR(12 downto 0); dina: IN std_logic_VECTOR(63 downto 0); clkb: IN std_logic; addrb: IN std_logic_VECTOR(12 downto 0); doutb: OUT std_logic_VECTOR(63 downto 0)); end component; -- Synplicity black box declaration attribute syn_black_box : boolean; attribute syn_black_box of multishot_dpram: component is true; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ -- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : multishot_dpram port map ( clka => clka, wea => wea, addra => addra, dina => dina, clkb => clkb, addrb => addrb, doutb => doutb); -- INST_TAG_END ------ End INSTANTIATION Template ------------ -- You must compile the wrapper file multishot_dpram.vhd when simulating -- the core, multishot_dpram. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help".