CERN FMC ADC 100M 14b 4cha solderpad
cern-fmc-adc-100m-14b-4cha / hdl / adc / rtl / fmc_adc_100Ms_csr.vhd
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-- Title : Wishbone slave core for FMC ADC 100MS/s core registers
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-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Tue Aug 30 19:24:48 2011
-- Standard : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fmc_adc_100Ms_csr is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
fs_clk_i : in std_logic;
-- Ports for PASS_THROUGH field: 'State machine commands' in reg: 'Control register'
fmc_adc_core_ctl_fsm_cmd_o : out std_logic_vector(1 downto 0);
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
-- Port for BIT field: 'FMC Si750 output enable' in reg: 'Control register'
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
-- Port for BIT field: 'Offset DACs clear (active low)' in reg: 'Control register'
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) MONOSTABLE field: 'Manual serdes bitslip' in reg: 'Control register'
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
-- Port for BIT field: 'Enable test data' in reg: 'Control register'
fmc_adc_core_ctl_test_data_en_o : out std_logic;
-- Port for BIT field: 'Manual TRIG LED' in reg: 'Control register'
fmc_adc_core_ctl_trig_led_o : out std_logic;
-- Port for BIT field: 'Manual ACQ LED' in reg: 'Control register'
fmc_adc_core_ctl_acq_led_o : out std_logic;
-- Port for std_logic_vector field: 'State machine status' in reg: 'Status register'
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
-- Port for BIT field: 'SerDes PLL status' in reg: 'Status register'
fmc_adc_core_sta_serdes_pll_i : in std_logic;
-- Port for BIT field: 'SerDes synchronization status' in reg: 'Status register'
fmc_adc_core_sta_serdes_synced_i : in std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'External hardware trigger polarity' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_ext_trig_pol_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger enable' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_en_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Software trigger enable' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_sw_trig_en_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel selection for internal trigger' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'Dummy' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_dummy_o : out std_logic_vector(9 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Threshold for internal trigger' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_thres_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger delay value' in reg: 'Trigger delay'
fmc_adc_core_trig_dly_o : out std_logic_vector(31 downto 0);
-- Ports for asynchronous (clock: fs_clk_i) PASS_THROUGH field: 'Software trigger' in reg: 'Software trigger'
fmc_adc_core_sw_trig_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sw_trig_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Number of shots' in reg: 'Number of shots'
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger UTC tag (LSBs)' in reg: 'Trigger UTC tag (LSBs)'
fmc_adc_core_trig_utc_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger UTC tag (MSBs)' in reg: 'Trigger UTC tag (MSBs)'
fmc_adc_core_trig_utc_h_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Start UTC tag (LSBs)' in reg: 'Start UTC tag (LSBs)'
fmc_adc_core_start_utc_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Start UTC tag (MSBs)' in reg: 'Start UTC tag (MSBs)'
fmc_adc_core_start_utc_h_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Stop UTC tag (LSBs)' in reg: 'Stop UTC tag (LSBs)'
fmc_adc_core_stop_utc_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Stop UTC tag (MSBs)' in reg: 'Stop UTC tag (MSBs)'
fmc_adc_core_stop_utc_h_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate'
fmc_adc_core_sr_deci_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Pre-trigger samples' in reg: 'Pre-trigger samples'
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Post-trigger samples' in reg: 'Post-trigger samples'
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Sample counter' in reg: 'Sample counter'
fmc_adc_core_samp_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 1' in reg: 'Solid state relays control for channel 1'
fmc_adc_core_ch1_ssr_o : out std_logic_vector(6 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 1 current value' in reg: 'Channel 1 current value'
fmc_adc_core_ch1_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 2' in reg: 'Solid state relays control for channel 2'
fmc_adc_core_ch2_ssr_o : out std_logic_vector(6 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 2 current value' in reg: 'Channel 2 current value'
fmc_adc_core_ch2_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 3' in reg: 'Solid state relays control for channel 3'
fmc_adc_core_ch3_ssr_o : out std_logic_vector(6 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 3 current value' in reg: 'Channel 3 current value'
fmc_adc_core_ch3_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 4' in reg: 'Solid state relays control for channel 4'
fmc_adc_core_ch4_ssr_o : out std_logic_vector(6 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 4 current value' in reg: 'Channel 4 current value'
fmc_adc_core_ch4_val_i : in std_logic_vector(15 downto 0)
);
end fmc_adc_100Ms_csr;
architecture syn of fmc_adc_100Ms_csr is
signal fmc_adc_core_ctl_fmc_clk_oe_int : std_logic ;
signal fmc_adc_core_ctl_offset_dac_clr_n_int : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_int : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_int_delay : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync0 : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync1 : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_core_ctl_test_data_en_int : std_logic ;
signal fmc_adc_core_ctl_trig_led_int : std_logic ;
signal fmc_adc_core_ctl_acq_led_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_ext_trig_pol_int : std_logic ;
signal fmc_adc_core_trig_cfg_ext_trig_pol_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_ext_trig_pol_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_en_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_en_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_en_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_sw_trig_en_int : std_logic ;
signal fmc_adc_core_trig_cfg_sw_trig_en_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_sw_trig_en_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_int : std_logic_vector(1 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_sel_swb : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_delay : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s0 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s1 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_core_trig_cfg_dummy_int : std_logic_vector(9 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_thres_swb : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_core_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sw_trig_wr_int : std_logic ;
signal fmc_adc_core_sw_trig_wr_int_delay : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync0 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync1 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync2 : std_logic ;
signal fmc_adc_core_shots_nb_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_sr_deci_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_sr_deci_swb : std_logic ;
signal fmc_adc_core_sr_deci_swb_delay : std_logic ;
signal fmc_adc_core_sr_deci_swb_s0 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s1 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch1_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_val_lwb : std_logic ;
signal fmc_adc_core_ch1_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch1_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch2_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch2_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_val_lwb : std_logic ;
signal fmc_adc_core_ch2_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch2_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch3_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch3_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_val_lwb : std_logic ;
signal fmc_adc_core_ch3_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch3_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch4_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch4_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_val_lwb : std_logic ;
signal fmc_adc_core_ch4_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch4_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fmc_adc_core_ctl_fsm_cmd_wr_o <= '0';
fmc_adc_core_ctl_fmc_clk_oe_int <= '0';
fmc_adc_core_ctl_offset_dac_clr_n_int <= '0';
fmc_adc_core_ctl_man_bitslip_int <= '0';
fmc_adc_core_ctl_man_bitslip_int_delay <= '0';
fmc_adc_core_ctl_test_data_en_int <= '0';
fmc_adc_core_ctl_trig_led_int <= '0';
fmc_adc_core_ctl_acq_led_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
fmc_adc_core_trig_cfg_sw_trig_en_int <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_int <= "00";
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_dummy_int <= "0000000000";
fmc_adc_core_trig_cfg_int_trig_thres_int <= "0000000000000000";
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '0';
fmc_adc_core_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_core_sw_trig_wr_int <= '0';
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_shots_nb_int <= "0000000000000000";
fmc_adc_core_sr_deci_int <= "0000000000000000";
fmc_adc_core_sr_deci_swb <= '0';
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ssr_int <= "0000000";
fmc_adc_core_ch1_val_lwb <= '0';
fmc_adc_core_ch1_val_lwb_delay <= '0';
fmc_adc_core_ch1_val_lwb_in_progress <= '0';
fmc_adc_core_ch2_ssr_int <= "0000000";
fmc_adc_core_ch2_val_lwb <= '0';
fmc_adc_core_ch2_val_lwb_delay <= '0';
fmc_adc_core_ch2_val_lwb_in_progress <= '0';
fmc_adc_core_ch3_ssr_int <= "0000000";
fmc_adc_core_ch3_val_lwb <= '0';
fmc_adc_core_ch3_val_lwb_delay <= '0';
fmc_adc_core_ch3_val_lwb_in_progress <= '0';
fmc_adc_core_ch4_ssr_int <= "0000000";
fmc_adc_core_ch4_val_lwb <= '0';
fmc_adc_core_ch4_val_lwb_delay <= '0';
fmc_adc_core_ch4_val_lwb_in_progress <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
fmc_adc_core_ctl_fsm_cmd_wr_o <= '0';
ack_in_progress <= '0';
else
fmc_adc_core_ctl_fsm_cmd_wr_o <= '0';
fmc_adc_core_ctl_man_bitslip_int <= fmc_adc_core_ctl_man_bitslip_int_delay;
fmc_adc_core_ctl_man_bitslip_int_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb <= fmc_adc_core_trig_cfg_int_trig_sel_swb_delay;
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb <= fmc_adc_core_trig_cfg_int_trig_thres_swb_delay;
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '0';
fmc_adc_core_sw_trig_wr_int <= fmc_adc_core_sw_trig_wr_int_delay;
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_sr_deci_swb <= fmc_adc_core_sr_deci_swb_delay;
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_ch1_val_lwb <= fmc_adc_core_ch1_val_lwb_delay;
fmc_adc_core_ch1_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch1_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_val_int;
fmc_adc_core_ch1_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch2_val_lwb <= fmc_adc_core_ch2_val_lwb_delay;
fmc_adc_core_ch2_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch2_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_val_int;
fmc_adc_core_ch2_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch3_val_lwb <= fmc_adc_core_ch3_val_lwb_delay;
fmc_adc_core_ch3_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch3_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_val_int;
fmc_adc_core_ch3_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch4_val_lwb <= fmc_adc_core_ch4_val_lwb_delay;
fmc_adc_core_ch4_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch4_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_val_int;
fmc_adc_core_ch4_val_lwb_in_progress <= '0';
end if;
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
fmc_adc_core_ctl_fsm_cmd_wr_o <= '1';
fmc_adc_core_ctl_fmc_clk_oe_int <= wrdata_reg(2);
fmc_adc_core_ctl_offset_dac_clr_n_int <= wrdata_reg(3);
fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4);
fmc_adc_core_ctl_man_bitslip_int_delay <= wrdata_reg(4);
fmc_adc_core_ctl_test_data_en_int <= wrdata_reg(5);
fmc_adc_core_ctl_trig_led_int <= wrdata_reg(6);
fmc_adc_core_ctl_acq_led_int <= wrdata_reg(7);
else
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(5) <= fmc_adc_core_ctl_test_data_en_int;
rddata_reg(6) <= fmc_adc_core_ctl_trig_led_int;
rddata_reg(7) <= fmc_adc_core_ctl_acq_led_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
else
rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_cfg_hw_trig_sel_int <= wrdata_reg(0);
fmc_adc_core_trig_cfg_ext_trig_pol_int <= wrdata_reg(1);
fmc_adc_core_trig_cfg_hw_trig_en_int <= wrdata_reg(2);
fmc_adc_core_trig_cfg_sw_trig_en_int <= wrdata_reg(3);
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(5 downto 4);
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '1';
fmc_adc_core_trig_cfg_dummy_int <= wrdata_reg(15 downto 6);
fmc_adc_core_trig_cfg_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '1';
else
rddata_reg(0) <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
rddata_reg(1) <= fmc_adc_core_trig_cfg_ext_trig_pol_int;
rddata_reg(2) <= fmc_adc_core_trig_cfg_hw_trig_en_int;
rddata_reg(3) <= fmc_adc_core_trig_cfg_sw_trig_en_int;
rddata_reg(5 downto 4) <= fmc_adc_core_trig_cfg_int_trig_sel_int;
rddata_reg(15 downto 6) <= fmc_adc_core_trig_cfg_dummy_int;
rddata_reg(31 downto 16) <= fmc_adc_core_trig_cfg_int_trig_thres_int;
end if;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_dly_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_trig_dly_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
fmc_adc_core_sw_trig_wr_int <= '1';
fmc_adc_core_sw_trig_wr_int_delay <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
fmc_adc_core_shots_nb_int <= wrdata_reg(15 downto 0);
else
rddata_reg(15 downto 0) <= fmc_adc_core_shots_nb_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_trig_utc_l_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_trig_utc_h_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_start_utc_l_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_start_utc_h_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_stop_utc_l_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_stop_utc_h_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
fmc_adc_core_sr_deci_int <= wrdata_reg(15 downto 0);
fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1';
else
rddata_reg(15 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
fmc_adc_core_pre_samples_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_pre_samples_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
fmc_adc_core_post_samples_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_post_samples_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_samp_cnt_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_ssr_int <= wrdata_reg(6 downto 0);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch1_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
else
fmc_adc_core_ch1_val_lwb <= '1';
fmc_adc_core_ch1_val_lwb_delay <= '1';
fmc_adc_core_ch1_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_ssr_int <= wrdata_reg(6 downto 0);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch2_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
else
fmc_adc_core_ch2_val_lwb <= '1';
fmc_adc_core_ch2_val_lwb_delay <= '1';
fmc_adc_core_ch2_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_ssr_int <= wrdata_reg(6 downto 0);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch3_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10101" =>
if (wb_we_i = '1') then
else
fmc_adc_core_ch3_val_lwb <= '1';
fmc_adc_core_ch3_val_lwb_delay <= '1';
fmc_adc_core_ch3_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_ssr_int <= wrdata_reg(6 downto 0);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch4_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
else
fmc_adc_core_ch4_val_lwb <= '1';
fmc_adc_core_ch4_val_lwb_delay <= '1';
fmc_adc_core_ch4_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- State machine commands
-- pass-through field: State machine commands in register: Control register
fmc_adc_core_ctl_fsm_cmd_o <= wrdata_reg(1 downto 0);
-- FMC Si750 output enable
fmc_adc_core_ctl_fmc_clk_oe_o <= fmc_adc_core_ctl_fmc_clk_oe_int;
-- Offset DACs clear (active low)
fmc_adc_core_ctl_offset_dac_clr_n_o <= fmc_adc_core_ctl_offset_dac_clr_n_int;
-- Manual serdes bitslip
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ctl_man_bitslip_o <= '0';
fmc_adc_core_ctl_man_bitslip_sync0 <= '0';
fmc_adc_core_ctl_man_bitslip_sync1 <= '0';
fmc_adc_core_ctl_man_bitslip_sync2 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ctl_man_bitslip_sync0 <= fmc_adc_core_ctl_man_bitslip_int;
fmc_adc_core_ctl_man_bitslip_sync1 <= fmc_adc_core_ctl_man_bitslip_sync0;
fmc_adc_core_ctl_man_bitslip_sync2 <= fmc_adc_core_ctl_man_bitslip_sync1;
fmc_adc_core_ctl_man_bitslip_o <= fmc_adc_core_ctl_man_bitslip_sync2 and (not fmc_adc_core_ctl_man_bitslip_sync1);
end if;
end process;
-- Enable test data
fmc_adc_core_ctl_test_data_en_o <= fmc_adc_core_ctl_test_data_en_int;
-- Manual TRIG LED
fmc_adc_core_ctl_trig_led_o <= fmc_adc_core_ctl_trig_led_int;
-- Manual ACQ LED
fmc_adc_core_ctl_acq_led_o <= fmc_adc_core_ctl_acq_led_int;
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
-- Hardware trigger selection
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, bus_clock_int <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_hw_trig_sel_o <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_sync0 <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_hw_trig_sel_sync0 <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
fmc_adc_core_trig_cfg_hw_trig_sel_sync1 <= fmc_adc_core_trig_cfg_hw_trig_sel_sync0;
fmc_adc_core_trig_cfg_hw_trig_sel_o <= fmc_adc_core_trig_cfg_hw_trig_sel_sync1;
end if;
end process;
-- External hardware trigger polarity
-- synchronizer chain for field : External hardware trigger polarity (type RW/RO, bus_clock_int <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_ext_trig_pol_o <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_sync0 <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_ext_trig_pol_sync0 <= fmc_adc_core_trig_cfg_ext_trig_pol_int;
fmc_adc_core_trig_cfg_ext_trig_pol_sync1 <= fmc_adc_core_trig_cfg_ext_trig_pol_sync0;
fmc_adc_core_trig_cfg_ext_trig_pol_o <= fmc_adc_core_trig_cfg_ext_trig_pol_sync1;
end if;
end process;
-- Hardware trigger enable
-- synchronizer chain for field : Hardware trigger enable (type RW/RO, bus_clock_int <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_hw_trig_en_o <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_sync0 <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_hw_trig_en_sync0 <= fmc_adc_core_trig_cfg_hw_trig_en_int;
fmc_adc_core_trig_cfg_hw_trig_en_sync1 <= fmc_adc_core_trig_cfg_hw_trig_en_sync0;
fmc_adc_core_trig_cfg_hw_trig_en_o <= fmc_adc_core_trig_cfg_hw_trig_en_sync1;
end if;
end process;
-- Software trigger enable
-- synchronizer chain for field : Software trigger enable (type RW/RO, bus_clock_int <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_sw_trig_en_o <= '0';
fmc_adc_core_trig_cfg_sw_trig_en_sync0 <= '0';
fmc_adc_core_trig_cfg_sw_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_sw_trig_en_sync0 <= fmc_adc_core_trig_cfg_sw_trig_en_int;
fmc_adc_core_trig_cfg_sw_trig_en_sync1 <= fmc_adc_core_trig_cfg_sw_trig_en_sync0;
fmc_adc_core_trig_cfg_sw_trig_en_o <= fmc_adc_core_trig_cfg_sw_trig_en_sync1;
end if;
end process;
-- Channel selection for internal trigger
-- asynchronous std_logic_vector register : Channel selection for internal trigger (type RW/RO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_int_trig_sel_swb_s0 <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb_s1 <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb_s2 <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_o <= "00";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_int_trig_sel_swb_s0 <= fmc_adc_core_trig_cfg_int_trig_sel_swb;
fmc_adc_core_trig_cfg_int_trig_sel_swb_s1 <= fmc_adc_core_trig_cfg_int_trig_sel_swb_s0;
fmc_adc_core_trig_cfg_int_trig_sel_swb_s2 <= fmc_adc_core_trig_cfg_int_trig_sel_swb_s1;
if ((fmc_adc_core_trig_cfg_int_trig_sel_swb_s2 = '0') and (fmc_adc_core_trig_cfg_int_trig_sel_swb_s1 = '1')) then
fmc_adc_core_trig_cfg_int_trig_sel_o <= fmc_adc_core_trig_cfg_int_trig_sel_int;
end if;
end if;
end process;
-- Dummy
fmc_adc_core_trig_cfg_dummy_o <= fmc_adc_core_trig_cfg_dummy_int;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_int_trig_thres_swb_s0 <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb_s1 <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb_s2 <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_int_trig_thres_swb_s0 <= fmc_adc_core_trig_cfg_int_trig_thres_swb;
fmc_adc_core_trig_cfg_int_trig_thres_swb_s1 <= fmc_adc_core_trig_cfg_int_trig_thres_swb_s0;
fmc_adc_core_trig_cfg_int_trig_thres_swb_s2 <= fmc_adc_core_trig_cfg_int_trig_thres_swb_s1;
if ((fmc_adc_core_trig_cfg_int_trig_thres_swb_s2 = '0') and (fmc_adc_core_trig_cfg_int_trig_thres_swb_s1 = '1')) then
fmc_adc_core_trig_cfg_int_trig_thres_o <= fmc_adc_core_trig_cfg_int_trig_thres_int;
end if;
end if;
end process;
-- Trigger delay value
fmc_adc_core_trig_dly_o <= fmc_adc_core_trig_dly_int;
-- Software trigger
-- pass-through field: Software trigger in register: Software trigger
fmc_adc_core_sw_trig_o <= wrdata_reg(31 downto 0);
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_sw_trig_wr_sync0 <= '0';
fmc_adc_core_sw_trig_wr_sync1 <= '0';
fmc_adc_core_sw_trig_wr_sync2 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_sw_trig_wr_sync0 <= fmc_adc_core_sw_trig_wr_int;
fmc_adc_core_sw_trig_wr_sync1 <= fmc_adc_core_sw_trig_wr_sync0;
fmc_adc_core_sw_trig_wr_sync2 <= fmc_adc_core_sw_trig_wr_sync1;
fmc_adc_core_sw_trig_wr_o <= fmc_adc_core_sw_trig_wr_sync1 and (not fmc_adc_core_sw_trig_wr_sync2);
end if;
end process;
-- Number of shots
fmc_adc_core_shots_nb_o <= fmc_adc_core_shots_nb_int;
-- Trigger UTC tag (LSBs)
-- Trigger UTC tag (MSBs)
-- Start UTC tag (LSBs)
-- Start UTC tag (MSBs)
-- Stop UTC tag (LSBs)
-- Stop UTC tag (MSBs)
-- Sample rate decimation
-- asynchronous std_logic_vector register : Sample rate decimation (type RW/RO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_sr_deci_swb_s0 <= '0';
fmc_adc_core_sr_deci_swb_s1 <= '0';
fmc_adc_core_sr_deci_swb_s2 <= '0';
fmc_adc_core_sr_deci_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_sr_deci_swb_s0 <= fmc_adc_core_sr_deci_swb;
fmc_adc_core_sr_deci_swb_s1 <= fmc_adc_core_sr_deci_swb_s0;
fmc_adc_core_sr_deci_swb_s2 <= fmc_adc_core_sr_deci_swb_s1;
if ((fmc_adc_core_sr_deci_swb_s2 = '0') and (fmc_adc_core_sr_deci_swb_s1 = '1')) then
fmc_adc_core_sr_deci_o <= fmc_adc_core_sr_deci_int;
end if;
end if;
end process;
-- Pre-trigger samples
fmc_adc_core_pre_samples_o <= fmc_adc_core_pre_samples_int;
-- Post-trigger samples
fmc_adc_core_post_samples_o <= fmc_adc_core_post_samples_int;
-- Sample counter
-- Solid state relays control for channel 1
fmc_adc_core_ch1_ssr_o <= fmc_adc_core_ch1_ssr_int;
-- Channel 1 current value
-- asynchronous std_logic_vector register : Channel 1 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch1_val_lwb_s0 <= '0';
fmc_adc_core_ch1_val_lwb_s1 <= '0';
fmc_adc_core_ch1_val_lwb_s2 <= '0';
fmc_adc_core_ch1_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch1_val_lwb_s0 <= fmc_adc_core_ch1_val_lwb;
fmc_adc_core_ch1_val_lwb_s1 <= fmc_adc_core_ch1_val_lwb_s0;
fmc_adc_core_ch1_val_lwb_s2 <= fmc_adc_core_ch1_val_lwb_s1;
if ((fmc_adc_core_ch1_val_lwb_s1 = '1') and (fmc_adc_core_ch1_val_lwb_s2 = '0')) then
fmc_adc_core_ch1_val_int <= fmc_adc_core_ch1_val_i;
end if;
end if;
end process;
-- Solid state relays control for channel 2
fmc_adc_core_ch2_ssr_o <= fmc_adc_core_ch2_ssr_int;
-- Channel 2 current value
-- asynchronous std_logic_vector register : Channel 2 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch2_val_lwb_s0 <= '0';
fmc_adc_core_ch2_val_lwb_s1 <= '0';
fmc_adc_core_ch2_val_lwb_s2 <= '0';
fmc_adc_core_ch2_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch2_val_lwb_s0 <= fmc_adc_core_ch2_val_lwb;
fmc_adc_core_ch2_val_lwb_s1 <= fmc_adc_core_ch2_val_lwb_s0;
fmc_adc_core_ch2_val_lwb_s2 <= fmc_adc_core_ch2_val_lwb_s1;
if ((fmc_adc_core_ch2_val_lwb_s1 = '1') and (fmc_adc_core_ch2_val_lwb_s2 = '0')) then
fmc_adc_core_ch2_val_int <= fmc_adc_core_ch2_val_i;
end if;
end if;
end process;
-- Solid state relays control for channel 3
fmc_adc_core_ch3_ssr_o <= fmc_adc_core_ch3_ssr_int;
-- Channel 3 current value
-- asynchronous std_logic_vector register : Channel 3 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch3_val_lwb_s0 <= '0';
fmc_adc_core_ch3_val_lwb_s1 <= '0';
fmc_adc_core_ch3_val_lwb_s2 <= '0';
fmc_adc_core_ch3_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch3_val_lwb_s0 <= fmc_adc_core_ch3_val_lwb;
fmc_adc_core_ch3_val_lwb_s1 <= fmc_adc_core_ch3_val_lwb_s0;
fmc_adc_core_ch3_val_lwb_s2 <= fmc_adc_core_ch3_val_lwb_s1;
if ((fmc_adc_core_ch3_val_lwb_s1 = '1') and (fmc_adc_core_ch3_val_lwb_s2 = '0')) then
fmc_adc_core_ch3_val_int <= fmc_adc_core_ch3_val_i;
end if;
end if;
end process;
-- Solid state relays control for channel 4
fmc_adc_core_ch4_ssr_o <= fmc_adc_core_ch4_ssr_int;
-- Channel 4 current value
-- asynchronous std_logic_vector register : Channel 4 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch4_val_lwb_s0 <= '0';
fmc_adc_core_ch4_val_lwb_s1 <= '0';
fmc_adc_core_ch4_val_lwb_s2 <= '0';
fmc_adc_core_ch4_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch4_val_lwb_s0 <= fmc_adc_core_ch4_val_lwb;
fmc_adc_core_ch4_val_lwb_s1 <= fmc_adc_core_ch4_val_lwb_s0;
fmc_adc_core_ch4_val_lwb_s2 <= fmc_adc_core_ch4_val_lwb_s1;
if ((fmc_adc_core_ch4_val_lwb_s1 = '1') and (fmc_adc_core_ch4_val_lwb_s2 = '0')) then
fmc_adc_core_ch4_val_int <= fmc_adc_core_ch4_val_i;
end if;
end if;
end process;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;